1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and, more particularly, to a nonvolatile semiconductor memory device that can increase the speed of bulk read operations and reduce bit-line pitches for the purpose of increasing the memory capacity.
2. Description of the Prior Art
A conventional nonvolatile semiconductor memory device of this kind, such as flash memory, is described in the 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp.61-62. The operations of this conventional flash memory--(1) read, (2) write and (3) erase--are described by referring to FIG. 9 of the present specification.
FIG. 9 shows an essential circuit of one memory cell connected to a word line and a bit line. In the figure, reference symbol MC represents a memory cell having a floating gate, and 10-17 represent N-channel MOS transistors that perform switching operations (hereinafter referred to simply as NMOS switches). In the following description, each NMOS switch is called by the reference name of a signal line that is connected to its gate for control.
(1) Read Operation
The read operation is performed by checking the current flowing through the memory cell MC to determine whether the memory cell MC is in the "1" or "0" state. In FIG. 9, the voltages of a signal line PRC and a signal line TR are held high to turn on NMOS switches 13, 15 and precharge a bit line BL and a sense & latch circuit SL to a voltage of a common source line VSA, after which the voltages of the signal line PRC and the signal line TR are lowered to turn off the NMOS switches 13, 15.
Next, a word line WL is supplied with a power supply voltage Vcc (not shown) and then three signal lines ST1, ST2 and TR are held high in voltage to turn on the corresponding NMOS switches 10, 11 and 15 to store a voltage change in the bit line BL corresponding to the cell information temporarily in the sense & latch circuit SL provided for each bit line.
Then, an NMOS switch 17 provided on each bit line BL is turned on by a line SW to output the information held in the memory cell MC onto the line 10.
(2) Write Operation
The write operation is performed as follows. First, information "1" or "0" is fed from the line IO through the NMOS switch SW to the sense & latch circuit SL where it is held. When "1" is held in the sense & latch circuit SL, because the NMOS switch 16 is on, the turning on of the NMOS switch PG causes the bit line BL to be precharged to 4 V, the voltage of the common source line VSA. When "0" is held in the sense & latch circuit SL, the NMOS switch 16 remains turned off and the bit line BL is not precharged.
Next, the voltage of the word line WL is set to -9 V and the NMOS switches TR and ST2 are turned on. At this time, the voltage of the bit line connected to the sense & latch circuit SL where information "1" is held is precharged to 4 V, whereas the voltage of the bit line connected to the sense & latch circuit SL where information "0" is held is not precharged and remains 0 V. Hence, the memory cell MC, which is connected to the sense & latch circuit SL where the write information "1" is held, is written with information "1."
Then, an NMOS switch DDC is turned on to connect the bit line BL to a common source V2 to discharge the bit line BL. The bit line BL connected to the sense & latch circuit SL is again precharged by turning on the NMOS switch PG according to whether the information held in the sense & latch circuit SL is "1" or "0". When the information held in the sense & latch circuit SL is "1," the NMOS switch 16 is on, so that the bit line BL is precharged to 1 V again by setting the voltage of a common source VSA to 1 V. When information held is "0," the NMOS switch 16 remains turned off leaving the bit line BL unprecharged.
Next, a verify operation is performed to check if the write operation has been successfully completed. The verify operation sets the voltage of the word line WL to 1.5 V and turns on NMOS switches ST1, ST2 and then NMOS switch TR. When the sense & latch circuit SL holds information "1" and the threshold of the written memory cell MC is lower than 1.5 V, the memory cell MC is turned on by the word line voltage of 1.5 V to lower the voltage of the bit line BL, causing the information "1" held in the sense & latch circuit SL to change to "0." This is taken as a verification that the information was written into the memory cell MC, thus terminating the write operation on the memory cell MC. If, after the write operation, the threshold of the memory cell MC is found to be equal to or greater than 1.5 V, the information "1" held in the sense & latch circuit SL remains as is. This causes the write and verify operations on the memory cell MC to be repeated until the threshold of the memory cell MC becomes lower than 1.5 V and the information held in the sense & latch circuit SL changes from "1" to "0."
(3) Erase Operation
The erase operation is performed one word line at a time. The voltage of the word line WL is set at 12 V, the substrate (not shown) is applied with 4 V, the signal line ST1 for NMOS switch 10 is set to the power supply voltage Vcc, the common source line V1 connected to the source of the NMOS switch 10 is set to -4 V, the gate voltages of the NMOS switches DDC, ST2 are set to 0 V, and the voltage of the common source line V2 connected to the source of the NMOS switch DDC is set to 0 V. This operation causes the bit line BL to float, thus performing the erase operation.
In FIG. 9, a signal line SET is used to turn on or off an NMOS switch 18 that drives the sense & latch circuit SL.
Further, the conventional flash memories have yet to employ a DC-based correction measure for flaws caused by shorting of bit lines.
The above-mentioned conventional flash memory has a configuration whereby the read operation is performed one word line at a time, i.e., after one word line has been read out, the sense & latch circuit is reset to discharge the bit line and the sense circuit and then the bit line and the sense & latch circuit are precharged again before the next word line is selected for reading. This operation is repeated for all word lines successively to read the contents of the memory, so that as the memory capacity increases the time taken for precharging and discharging increases, making it more difficult to perform the read operation at high speed.
In the configuration in which a sense & latch circuit is provided for each bit line, as in the conventional flash memory, there is a problem that while the miniaturization of memory cells for increased memory capacity reduces the layout interval of bit lines, the sense & latch circuits cannot be reduced in size by as much as are the pitches of the bit lines.
Further, although a DC-based flaw correction measure needs to be prepared to deal with defects that are caused by shortcircuiting between reduced-interval bit lines as the miniaturization of memory cells progresses, the conventional flash memories have yet to use such a correction measure.
It is therefore a primary object of this invention to provide a nonvolatile semiconductor memory device, which allows fast reading of a large-capacity memory and which can easily accommodate a DC-based flaw correction measure designed to correct defects such as caused by shortcircuits between bit lines whose intervals have decreased with miniaturization of memory cells.
Another object of this invention is to provide a nonvolatile semiconductor memory device, which can reduce the pitches of the sense & latch circuits to miniaturize memory cells for increased capacity of memory and can easily accommodate a DC-based flaw correction measure designed to repair defects such as caused by shortcircuits between bit lines whose intervals have decreased with miniaturization of memory cells.